`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:01:23 08/23/2012
// Design Name:   Projecto2
// Module Name:   C:/Users/Maria Victoria/workspace/Projecto2/test.v
// Project Name:  Projecto2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Projecto2
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test;

	// Inputs
	reg clock;
	reg reset;

	// Outputs
	wire clock1hz;

	// Instantiate the Unit Under Test (UUT)
	Projecto2 uut (
		.clock(clock), 
		.reset(reset),  
		.clock1hz(clock1hz)
	);
	initial begin
		// Initialize Inputs
		clock=0;
		reset = 1;
		#100
		reset = 0;
	end
	always #20 clock <= ~clock;
	
      
endmodule

